This disclosure relates to data buffer control circuit for semiconductor memory apparatuses.
Semiconductor memories have been continuously evolving toward higher and higher integration densities and ever increasingly swifter data rates for the purpose of enhancing systemic performance. The requirement for higher data rate of semiconductor memories has contributed to the great advancement of synchronous dynamic random access memories (synchronous DRAMs) that are operable in sync with system clocks.
Traditional synchronous DRAMs had a limit to enlarging a bandwidth between themselves and DRAM controllers, i.e., an amount of data input/output per unit time, because data input/output could be conducted in one clock cycle of a system clock. In recent years, dual-data-rate (DDR) synchronous DRAMs (DDR SDRAMs) have been developed to more enhance data rates, in which data are input/output in sync with both raising and falling edges of system clocks. The DDR SDRAMs are usually employing data strobe signals in order to reduce timing margin loss by a timing skew between them, access time gaps by variations of process, voltage and temperature (PVT variation), and differences of propagation delays between memory controllers and memory modules.
In the meantime, a parameter tQSS is defined in a DDR SDRAM for the purpose of assuring a reliable writing operation. The tQSS means a delay time from a rising edge of a system clock (tCK) at which a write command is input into the DDR SDRAM until a first rising edge of the data strobe signal. In the standard specification, the minimum clock cycle time of tQSS is defined in 0.75tCK and the maximum clock cycle time is defined in 1.25tCK. Therefore, the DDR SDRAM must normally complete a data writing operation in the minimum time of 0.75tCK or in the maximum time 1.25tCK.
FIG. 1 shows a general process of data buffer control operation. The data buffer control operation shown in FIG. 1 is for generating a buffer enable signal to enable a data buffer into which data is input during a writing mode with tQSS of the minimum cycle time 0.75tCK.
First, delayed command signals transition to a predetermined level combination (e.g., a first delayed command signal CSBD, a second delayed command signal RASB and a third delayed command signal CASB go to a low level, a high level and a low level, respectively) and a time A1 after setup times of the delayed command signals is set as an input time of a write command WT_CMD. Thus, in the writing mode, data should be input at a time A3 by tQSS set to 0.75tCK.
Next, a buffer enable signal BFREN1 for enabling the data buffer receiving data is activated to a low level at a time A2 in response to a control signal CON synchronized to a rising edge of an internal clock signal ICLK. The internal clock signal ICLK is generated in sync with a rising edge of an external clock signal CLK.
However, in the scheme of data buffer control operation, as a clock cycle time is being shortened with higher frequency of the semiconductor memory, it becomes more difficult in securing a sufficient operational margin between the time A2, at which the buffer enable signal BFREN1 is activated, and the time A3 at which data is input.